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1 for more information www.analog.com typical application features description dual channel prioritized powerpath controller the lt c ? 4418 connects one of two valid power supplies to a common output based on priority and validity. priority is defined by pin assignment, with v1 assigned the higher priority and v2 the lower priority. a power supply is defined as valid when its voltage has been within its overvoltage (ov) and undervoltage (uv) window continuously for at least the configured validation time. if the highest priority valid input falls out of the ov/uv window, the channel is immediately disconnected and the other valid input is con - nected to the common output. multiple lt c4418 s, as well as triple channel lt c4417 s, can be cascaded to provide switchover between more than two inputs. the lt c4418 incorporates fast non-overlap switching circuitry to prevent both reverse and cross conduction while minimizing output droop. the gate driver includes a 6v clamp to protect external mosfets. a controlled soft-start feature minimizes start-up inrush current. open drain valid outputs indicate the input supplies have been within their ov/uv window for the duration of the valida - tion time. the validation time can be disabled or adjusted using an external capacitor. applications n selects highest priority supply from two inputs n blocks reverse and cross conduction currents n wide operating voltage range : 2.5v to 40v n C 42v protection against reverse connection n 60v tolerant v1 , v2 inputs n adjustable input validation time n fast switchover minimizes output voltage droop n low 26a operating current n 1.5% input overvoltage/undervoltage protection n adjustable overvoltage/undervoltage hysteresis n cascadable for additional input supplies n 20- lead 4mm 4mm qfn package n industrial handheld instruments n high availability systems n battery backup systems n servers and computer peripherals all registered trademarks and trademarks are the property of their respective owners. v2 uv2 ov2 LTC4418 4418 ta01a vs1 g1 vs2 g2 1m 100nf 60.4k 226k 1m 33.2k 78.7k 470nf bat46wj m3 m4 47nf 698 100k 82f 1.25a max output v1 uv1 ov1 cas intv cc en shdn + fds4465 m1 m2 fds4465 5v sys 12v wall adapter gnd hys 255k tmr 1nf 100nf 100k valid1 valid2 v out priority switching from v1 to v2 document feedback lt c4418 rev a 2v/div 4418 ta01b v out 5v 13.8v 2ms/div i load = 1.25a c out = 82f v1 2v/div v2
2 for more information www.analog.com pin configuration absolute maximum ratings supply voltages v1 , v2 ..................................................... C 42v to 60v v out ....................................................... C 0.3v to 42v v s1 , v s2 ................................................ C 0.3v to 60v voltage from v1 , v2 to v out ....................... C 84v to 60v voltage from v s1 , v s2 to g1 , g2 ............... C 0.3v to 7. 5 v input voltages en, shdn .............................................. C 0.3v to 60v o v1 , o v2 , u v1 , u v2 , tmr ....................... C 0.3v to 6v hys ......................................................... C 0.3v to 1v intv cc .................................................. C 0.3v to 6.2v output voltages vali d1 , vali d2 ...................................... C 0.3v to 60v cas .......................................................... C 0.3v to 6v input currents o v1 , o v2 , u v1 , u v2 , hys, tmr, intv cc , en, shdn ............................................ C 3ma output currents vali d1 , vali d2 , cas .............................. C 2ma /+ 5ma operating ambient temperature range lt c4418 c ................................................ 0 c to 70 c lt c4418 i ............................................. C 40 c to 85 c storage temperature range .................. C 65 c to 150 c (notes 1, 2) aa a a a a a a r shdn valid1 valid2 a order information lead free finish tape and reel part marking* package description temperature range lt c4418 cuf#pbf lt c4418 cuf#trpbf 4418 20- lead ( 4mm 4mm ) plastic qfn 0 c to 70 c lt c4418 iuf#pbf lt c4418 iuf#trpbf 4418 20- lead ( 4mm 4mm ) plastic qfn C 40 c to 85 c consult adi marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a la bel on the shipping container. for more information on lead free part marking, go to : http : //www.linear.com/leadfree/ for more information on tape and reel specifications, go to : http : //www.linear.com/tapeandreel/ . some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. http : //www.linear.com/product/ lt c4418 #orderinfo lt c4418 rev a
3 for more information www.analog.com electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c . unless otherwise noted, v1 = v s1 = 12v and/or v2 = v s2 = 12v , v out = 12v , hys = gnd, cas = open, g1 = g2 = open. (notes 1, 2) symbol parameter conditions min typ max units start-up v1 , v2 , v out v1 , v2 , v out operating supply range l 2.5 40 v v intvcc intv cc voltage l 2.5 3.3 4 v i tot total supply current (sum of i vout , i v1 , i v2 , i v s1 , i v s2 ) shdn = 0v l l 26 22 52 44 a a i vout v out supply current l 17 34 a i v1 , i v2 v1 , v2 supply current (note 3) v out = 0v , en = 0v v out = 0v , shdn = 0v l l l 1.4 21 13 2.8 42 26 a a a i v s1 , i v s2 vs supply current channel on channel off l l 5.7 1.8 11.4 3.6 a a gate control ? v g open clamp voltage (vs C vg) v out = 11v , g1 = g2 = open l 5.4 6.2 6.7 v ? v g(source) sourcing clamp voltage (vs C vg) v out = 11v , i = C 10a l 5.8 6.6 7 v ? v g(sink) sinking clamp voltage (vs C vg) v out = 11v , i = 10a l 4.5 5.2 6 v i g(dn) gate pull-down current vg = 3v , vs floating l 28 60 120 ma ? v g(off) gate off threshold (vs C vg) v s1 = v s2 = 2.8v , v out = 11v , gate rising l 0.2 0.3 0.4 v r g(off) gate off resistance v1 or v2 = 12v , i g = C 10ma l 8 16 28 v rev reverse voltage threshold measure ( v1 or v2 ) C v out falling l 75 125 185 mv t g(switchover) break-before-make time v out = 11v , c gate = 10nf (note 4) l 1 2.7 4 s t p( shdn ) gate turn-off delay from shdn v out = 11v , falling edge shdn to g1 = v s1 C 3v or g2 = v s2 C 3v , c gate = 10nf l 0.3 0.7 1.4 s t p(en) gate turn-on/off delay from en v out = 11v , rising/falling en edge to g1 = v s1 C 3v or g2 = v s2 C 3v , c gate = 10nf l 0.3 0.7 1.4 s t ss soft-start timeout v out = 2v l 20 35 70 ms input/output pins v valid (ol) valid output low voltage i = 1ma , v1 or v2 = 2.5v , v out = 0v l 0.23 0.5 v v cas(oh) cas output high voltage i = C 1a , v1 , v2 , v out > 2.5v , uv = ov = en = 0v l 1.6 2.7 3.5 v v cas(ol) cas output low voltage i = 1ma , v1 or v2 = 2.5v , v out = 0v l 60 150 mv i cas cas pull-up current shdn = 0v , cas = 1v l C 10 C 20 C 40 a t cas(en) cas delay from v g(off) v out = 11v l 0.3 0.7 1.4 s v en(th) en threshold voltage en rising, v out = 11v l 0.6 1 1.4 v v shdn (th) shdn threshold voltage shdn rising l 0.6 1 1.4 v v shdn _en (hys) shdn , en threshold hysteresis 130 mv i ctrl shdn , en pull-up current shdn = en = 0v l C 1.5 C 3.2 C 5.5 a i leak shdn , en, vali d1 , vali d2 , cas leakage current shdn = en = vali d1 = vali d2 = 40v , cas = 5.5v l 1 a lt c4418 rev a
4 for more information www.analog.com electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c . unless otherwise noted, v1 = v s1 = 12v and/or v2 = v s2 = 12v , v out = 12v , hys = gnd, cas = open, g1 = g2 = open. (notes 1, 2) symbol parameter conditions min typ max units ov, uv protection circuitry v th ov/uv comparator threshold v out = 11v , ov rising, uv falling l 0.985 1 1.015 v v hys(int) ov/uv comparator hysteresis v out = 11v l 15 30 45 mv i leak ov/uv leakage current ov = 1.015v , uv = 0.985v l 10 na i ext external hysteresis current into/out of uv/ov pins i hys = C 400na i hys = C 4a l l 40 470 50 500 60 530 na na v hys hys voltage i hys = C 4a l 480 500 520 mv validation timer i tmr tmr pull-up current tmr pull-down current timer on, v tmr 600mv timer on, v tmr 1.6v l l C 1 1 C 2 2 C 3.5 3.5 a a t valid ov, uv validation time tmr = v intvcc ctmr = 1nf l l 2 9 3.5 16 7 32 s ms t valid (off) valid off delay from ov/uv fault uv or ov 10% overdrive, measure vali d1 or vali d2 rising edge l 2 3.5 7 s v th(tmroff) tmr disable voltage threshold measure v intvcc -v tmr , rising edge l 50 100 180 mv v th(tmrhys) tmr disable voltage hysteresis 120 mv note 1 : stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2 : all currents into pins are positive ; all voltages are referenced to gnd unless otherwise specified. note 3 : specification represents the diode-or d current of v1 or v2 input supplies. current is split evenly if both supplies are equal. note 4 : u v1 or u v2 driven below v th . time is measured from respective rising edge g1 crossing v s1 C 3v or g2 crossing v s2 C 3v to next valid priority falling edge g1 crossing v s1 C 3v or g2 crossing v s2 C 3v . lt c4418 rev a
5 for more information www.analog.com typical performance characteristics total enabled supply current vs supply voltage total shutdown supply current vs supply voltage i v1 , i v2 , i vout vs v2 supply voltage gate drive voltage vs temperature gate falling slew rate vs temperature gate rising slew rate vs temperature gate pull-down current vs gate voltage break before make time vs temperature valid delay off time vs temperature t a = 25 c , unless otherwise noted. lt c4418 rev a 30 18 gate falling slew rate (v/s) 4418 g05 v1 = 2.7v v1 = 5v v1 = 12v v1 = 40v v1 = 24v v1 = v2 c gate = 10nf temperature (c) 40 ?50 ?25 0 25 50 75 100 0 4 8 0 12 16 gate rising slew rate (v/s) 4418 g06 v1 = 2.7v v1 = 5v v1 = 12v, 24v, 40v v1 = v2 c gate = 10nf gate voltage (v) 0 5 0.5 1 1.5 2 2.5 3 3.5 0.01 0.1 1 10 10 100 gate pull?down current (ma) 4418 g07 90c 25c ?45c v1/v2 = 12v vs1/ vs2 = floating v out = 11.7v 15 temperature (c) ?50 ?25 0 25 50 75 100 1.5 2.0 20 2.5 3.0 3.5 t g(switchover) (s) 4418 g08 v1 = 40v v1 = 12v v1 = 3v v1 = v2 c gate = 10nf temperature (c) 25 ?50 ?25 0 25 50 75 100 2 3 4 30 5 6 7 valid delay time (s) 4418 g09 35 all supply vs and v out pins connected together 40 total enable supply current (a) 4418 g01 ?45c 90c 25c supply voltage (v) 0 10 20 ?45c 30 40 0 5 10 15 20 25 30 total supply current (a) 90c 4418 g02 all supply vs and v out pins connected together v2 voltage (v) ?40 ?30 ?20 ?10 0 10 20 25c 30 40 0 5 10 15 20 i v1-v2-vout(en) (a) 4418 g03 i vout supply voltage (v) i vs1 +i vs2 i v2 i v1 v1 = v s1 = v s2 = v out = 12v temperature (c) ?50 ?25 0 25 50 0 75 100 4.5 5.0 5.5 6.0 6.5 7.0 ?v g (v) 4418 g04 10 open i g = ?10a i g = 10a temperature (c) ?50 ?25 0 25 50 75 20 100 0 2 4 6 8 10 12 14 16
6 for more information www.analog.com typical performance characteristics t a = 25 c , unless otherwise noted. ov, uv threshold vs temperature validation time vs tmr capacitance ov, uv hysteresis current configuration intv cc vs input voltage ( v1 , v2 , v out ) vali d1 , vali d2 pull-down strength deglitched connection v out switching from higher to lower voltage v out switching from lower to higher voltage with inrush current limiting circuitry reverse voltage blocking lt c4418 rev a 50 v1 2v/div v2 2v/div 4418 g16 c out = 120f i load = 2a ?20v pch fds4465 v out 50s/div r s = 475 c s = 47nf c out = 120f i load = 2a ?20v pch fds4465 v1 75 4v/div v2 4v/div i v2 10a/div 4418 g17 v1 = +15v v1 = ?15v ?40v pch fdd4685 c out = 10f i load = 1a 2ms/div 100 v1 5v/div v2, v out 5v/div 4418 g18 0.96 0.97 0.98 0.99 1.00 1.01 1.02 v th 1.03 1.04 v th (v) 4418 g10 v1/2 = 12v c tmr (nf) 0.1 1 10 100 uv rising threshold 1k 1 10 100 1k 10k validation delay (ms) 4418 g11 i hys (na) 0 ov falling threshold 1000 2000 3000 4000 0 100 200 300 400 500 temperature (c) i ext (na) 4418 g12 input voltage (v) 0 8 16 24 32 40 0 ?50 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 intv cc (v) 4418 g13 ?25 90c 25c ?45c v1/v2 = 12v v out = 12v pull-up current (ma) 0 1 2 3 4 0 5 0 0.2 0.4 0.6 0.8 1.0 v valid (ol) (v) 4418 g14 v out 25 5ms/div c tmr = 1nf c out = 120f i load = 1a ?40a pch fds4685 v1 2v/div v2 2v/div 4418 g15 500s/div v out 2v/div
7 for more information www.analog.com pin functions tmr (pin 1) : validation timer. attach an external capacitor between tmr and gnd of at least 100pf to set a valida - tion time of 16ms /nf for both channels. connect tmr to intv cc to set a minimum validation time of 3.5s (fast mode). do not leave open. u v1 , u v2 (pins 2, 4) : undervoltage comparator inputs. falling voltages below 1v (v th ) trigger an undervoltage event, invalidating the respective input supply channel. connect u v1 and u v2 to a resistive divider between the respective v1 and v2 and ground to achieve the desired undervoltage threshold. the comparator hysteresis can be set internally to v hys(int) or set externally via the hys pin. connect unused pins to ground. o v1 , o v2 (pins 3, 5) : overvoltage comparator inputs. rising voltages above 1v (v th ) signal an overvoltage event, invalidating the respective input supply channel. connect o v1 and o v2 to an external resistive divider from its respective v1 and v2 to achieve the desired overvoltage threshold. the comparator hysteresis can be set internally to v hys(int) or set externally via the hys pin. connect unused pins to ground. vali d1 , vali d2 (pins 6, 7) : valid channel indicator out - puts. vali d1 and vali d2 are 40v rated, open drain outputs that pull low when the respective v1 and v2 are within the ov/uv window for at least the configured validation time and release when the respective v1 and v2 are outside the ov/uv window. connect a resistor between vali d1 and vali d2 and a desired supply, which may be v1 , v2 or v out , to provide the pull-up. leave open when not used. gnd (pin 8, exposed pad pin 21) : device ground. exposed pad may be left open or connected to device ground. cas (pin 9) : cascade output. digital output used for cas - cading multiple lt c4418 s and/or lt c4417 s. connect cas to en of another lt c4417 / lt c4418 to increase the number of multiplexed input supplies. cas is pulled up to intv cc by an internal 20a current source (i cas ) to indicate when all inputs are invalid, the external p-channel mosfets are determined to be off, and en is above v en(th) . cas also pulls high when shdn is driven below v shdn (th) . cas is pulled low when any input supply is within the ov/uv window for at least the configured validation time and shdn is above its threshold. cas also pulls low when en is driven below v en(th) . cas can be pulled up to voltages as high as 5.5v , independent of the input supply voltages. leave open if not used. intv cc (pin 10) : internal low voltage supply decoupling output. do not connect an external load current to intv cc . connect a 0.1f capacitor from this pin to gnd. g1 , g2 (pins 13, 11) : p-channel mosfet gate drive outputs. g1 and g2 are used to control external p-channel mosfets. when driven low, g1 and g2 are clamped 6.2v ( ? v g ) below their corresponding v s1 and v s2 . connect g1 and g2 to external p-channel mosfet gate pins. v s1 , v s2 (pins 14, 12) : external p-channel mosfet common source connection. the gate drivers use v s1 and v s2 to monitor the common source connection of the external p-channel mosfets. connect v s1 and v s2 to the respective common source connection of the p-channel mosfets. connect to ground when channel is not used. see applications information section for bypass capacitor recommendations. v out (pin 15) : output voltage supply and sense. v out is an output voltage sense pin used to prevent any input supply from connecting to the output if the output voltage is not below the input supply voltage by at least 125mv (v rev ). during normal operation, v out powers most of the internal circuitry when its voltage exceeds 2.475v . see applications information section for bypass capacitor recommendations. v2 (pin 16) : lower priority input supply. when v2 is within its user defined ov/uv window for the configured validation time, it is connected to v out via its external p-channel mosfets only if v1 does not meet its ov/uv requirements. connect v2 to ground when channel is not used. see applications information for bypass capacitor recommendations. v1 (pin 17) : higher priority input supply. when v1 is within its user defined ov/uv window for the configured validation time, it is connected to v out via its external p-channel mosfets. see applications information for bypass capacitor recommendations. lt c4418 rev a
8 for more information www.analog.com pin functions en (pin 18) : channel enable input. en is a 40v input that allows the user to quickly connect and disconnect channels without resetting the ov/uv validation timer. this feature is essential in cascading applications. when below 1v (v en(th) ), both external p-channel mosfets are driven off by pulling g1 and g2 to their respective v s1 and v s2 . when above v en(th) , the highest valid priority channel is connected to the output. en is pulled to intv cc with a 3.2a current source (i ctrl ) and can be pulled up externally to a maximum voltage of 40v . connect to intv cc when not used. shdn (pin 19) : shutdown input. driving shdn below v shdn (th) turns off all external p-channel mosfets, dis - ables the ov/uv comparators and resets the validation timers used to validate v1 and v2 . cas is pulled high to allow lower priority lt c4417 / lt c4418 s in a cascaded system to provide power to v out . driving shdn above 1v (v shdn (th) ) allows channels to validate and connect. shdn is pulled high to intv cc with a 3.2a current source (i ctrl ) and can be pulled up externally to a maximum voltage of 40v . connect to intv cc when not used. hys (pin 20) : ov/uv comparator hysteresis input. con - necting hys to ground sets a fixed hysteresis (v hys(int) ) for the ov and uv comparators. connecting a resistor, r hys , between hys and ground disables the internal hysteresis and sets a 63mv /r hys hysteresis current which is sourced from each o v1 and o v2 and sunk into each u v1 and u v2 pin. connect to gnd if not used. lt c4418 rev a
9 for more information www.analog.com block diagram + ? + ? + ? + ? + ? + ? + ? + ? lt c4418 rev a intv cc v out cas gnd validation timer ch1 valid hold ch off external switch on rev vgs 3.2a gate driver uv2 uv1 ov2 ov1 valid2 valid1 channel 1 channel 2 v2 intv cc v1 vs2 vs1 g2 4418 bd g1 prioritized nonoverlap control logic tmr uv ov 1v intv cc i ext v out int hys ext hys uv ov i ext 125mv 300mv intv cc i ext 1v 1.03v 6.2v 970mv 3.2a intv cc 1v intv cc oscillator shdn disable gatedrivers and reset validation timer disable gatedrivers hys hysteresis regulator v1 v2 en 20a intv cc
10 for more information www.analog.com timing diagram lt c4418 rev a t valid (off) t g(switchover) t p(en) t p(en) t p(shdn) shdn 4418 td g1 g2 valid2 valid1 uv2 uv1 en t valid
11 for more information www.analog.com operation the lt c4418 is an intelligent 40v dual channel powerpath ? switch that automatically connects one of two input sup - plies to a common output based on a channel s priority and validity. channel 1 is defined to be higher priority than channel 2 regardless of voltage levels. a channel s validity is user defined by a set of undervoltage (uv) and overvoltage (ov) comparators biased with a resistive divider off of the channel s input. connection is made by enhancing external back-to-back p-channel mosfets. un - like a diode-or, which always passes the highest supply voltage to the output, the lt c4418 lets one use a higher supply as a secondary for backup power. during normal operation the lt c4418 continuously moni - tors v1 and v2 through its respective uv and ov pins using precision overvoltage and undervoltage compara - tors. an input supply is defined valid when the voltage remains in the ov/uv window for at least the validation time, (t valid ). if the input supply connected to v1 falls out of the ov/uv window and remains outside for at least 3.5s (t valid (off) ) the channel is disconnected. v2 is then connected to the common output if it is within its ov/uv window. the lt c4418 always connects the higher priority v1 supply if it becomes valid regardless of the status of v2 . vali d1 and vali d2 pull low to indicate when the v1 and v2 input supplies are valid. hysteresis on the uv and ov inputs can be configured to be a fixed 3% or made adjustable. connecting the hys pin to ground sets the hysteresis on both channels to be 3% of the monitored voltage. connecting a resistor, r hys , between hys and ground forces 63mv /r hys current out of o v1 and o v2 and into u v1 and u v2 in order to create hysteresis when outside their respective ov/uv windows. the configuration of hys affects both channels. during channel transitions, monitoring circuitry prevents cross conduction between input supplies and reverse conduction from v out using a break-before-make archi - tecture. the vgs comparator monitors the disconnecting channel s gate pin voltage ( g1 or g2 ). when the gate voltage is 300mv ( ? v g(off) ) from its common source connection (v s1 or v s2 ), the vgs comparator latches the output to indicate the channel is off and allows the other valid priority input supply to connect to v out , preventing cross conduction between channels. to prevent reverse conduction from v out to v1 and v2 during channel switchover, the rev comparator monitors the connecting input supply ( v1 or v2 ) and v out . the rev comparator delays the connection until the output voltage droops lower than the input voltage by 120mv (v rev ). once activated, the lt c4418 gate driver pulls g1 or g2 down to 6.2v ( ? v g ) below its respective v s1 or v s2 with a strong pull-down current. after turning on, the gate driver holds the gates of the external p-channel mosfets at ? v g with a small pull-down current. to minimize inrush current at start-up, the gate driver soft-starts the first input supply to connect to v out at a rate of approximately 4v / ms terminating when any channel disconnects or 35ms elapses. once slew rate control has terminated, the gate driver returns to normal gate driving operation. when en is driven above 1v (v en(th) ) the highest valid priority input supply is connected to v out . when en is driven below v en(th) all channels are disconnected from v out and the lt c4418 continues to monitor the ov and uv pins indicating status with vali d1 and vali d2 . when shdn is pulled below 1v (v shdn (th) ) all channels are disconnected, ov and uv comparators are disabled and both channel validation timers are reset. a shdn low to high transition reactivates soft-start, provided v out drops below 2.3v before shdn is high. v out dropping below 1.7v also reactivates soft-start. when additional supplies need to be prioritized the part can work in conjunction with other lt c4417 s and/or lt c4418 s where the cas pin of the highest priority controller is con - nected to the en of the lower priority controller. if v out is allowed to fall below 1.7v , the next connecting input supply is soft-started. the lt c4418 has its own internally generated 3.3v rail (intv cc ) that provides power to internal circuits of the part. the intv cc rail is prioritized such that supply cur - rent comes from one of three prioritized sources ( v1 , v2 or v out ). an external capacitor must be connected between the intv cc pin and gnd to hold up the internal rail in the event of transients such as input supply shorts. lt c4418 rev a
12 for more information www.analog.com powerpath controllers are designed to connect one of several input supplies to a common output based on their priority and validity. the highest priority supply may not necessarily be the highest in voltage. while the applica - tion appears simple at first glance there are a few issues that must be accounted for when building an application. one issue is input supply inrush current during a channel switchover that occurs when charging a low esr output capacitor. inrush current dissipates significant power in the external p-channel mosfets. it also causes input voltage droop due to the input power supply s source impedance and the parasitic impedance of connectors, cables and pcb traces. input supply voltage droop can cause uv faults that trigger a phenomenon called motor-boating, where the input supply repeatedly connects and disconnects from the output. motor-boating can lead to component damage or undesirable/erratic circuit behavior. another issue is output voltage droop which occurs dur - ing the break-before-make time of a switchover between channels. ideally, there would be no disruption of the output voltage during a switchover. however, load current discharges the output capacitor during the break-before- make time resulting in output voltage droop. to ensure minimum output voltage droop, a large value, low esr capacitor is used to ride through this dead time. there is a trade-off between inrush current and output voltage droop. the following sections describe these challenges in more detail and explain component selection to properly manage them. note that input supply voltages denoted by sys are not hot-swappable, all other input supplies are hot-swappable. defining operation range the operation range for each lt c4418 channel is defined by an ov/uv window. an input supply must remain inside the ov/uv window for the ov/uv validation time, t valid , to become valid and connect to the output. both ov and uv thresholds include hysteresis which reduces the operat - ing window as shown in figure?1 . for example, v1 supply voltage must be greater than uv hys to exit the uv fault. if an ov fault occurs, the v1 supply voltage must return to a voltage lower than the ov hys voltage to exit the ov fault. reduced operating window ov/uv window ov uv v1 4418 f01 uv1 fault ov1 fault v1 valid1 ov hys uv hys figure?1. ov and uv thresholds and hysteresis voltage applications information the ov/uv window for each input supply is set by a resis - tive divider connected from the input supply to gnd. the most important consideration when setting the resistive divider values for the ov/uv window is to provide enough hysteresis to allow for input supply voltage droop due to inrush and load current during switchover. in addition to input supply droop take into consideration : 1. tolerance of the input supply 2. 1.5% ov/uv comparator threshold error 3. tolerance of external resistive divider 4. max i leak ov/uv pin leakage currents hysteresis for the ov and uv comparators is set via the hys pin. two options are available. connecting a resistor, r hys , between hys and gnd, as shown in figure?2 , sets the hysteresis current i hys that is sunk into u v1 and u v2 and sourced out of o v1 and o v2 . the value of r hys is calculated with : r h y s = 6 3 m v i e x t choose r hys to limit the hysteresis current in the range 50na to 500na . connecting hys to gnd, as shown in figure?3 , selects an internal 30mv fixed hysteresis, result - ing in 3% of the input supply range. lt c4418 rev a
13 for more information www.analog.com applications information figure?2. adjustable external ov/uv hysteresis figure?3. 3% internal hysteresis with optional filter capacitor and manual disconnect mosfet lt c4418 rev a r9 r8 r12 r11 i hys/8 i hys/8 m1 rp r hys t-resistive r3 connection dual- resistive connection alternate independent hysteresis uv1 ov1 ov1 uv1 r2 v1 uv1 gnd 1v 1v intv cc uv ov validation timer LTC4418 r1 v out valid1 hys 124k to 1.24m i hys v1 input supply ov1 4418 f02 r3 r2 r7 r1 m1 r p c uvf m2 v1 uv1 gnd 1v 1v r6 uv ov LTC4418 v out valid1 hys v1 input supply optional filter capacitor optional disconnect ov1 r5 1.03v 0.97v validation timer 4418 f03 r4 r10
14 for more information www.analog.com applications information refer to the design example for an explanation of the three-resistor configuration for setting ov/uv thresholds and hysteresis. independent ov and uv hysteresis values are available by separating the single string resistive divid - ers r1 , r2 and r3 , shown in figure?2 , into two resistive strings, r4 - r5 and r6 - r7 . in such a configuration, the top resistor defines the amount of hysteresis and the bottom resistor defines the threshold. r top and r bot are calculated using : r t o p = d e s i r e d h y s t e r e s i s i e x t r b o t = r t o p ( o v / u v t h r e s h o l d ) ? 1 when large independent hysteresis voltages are required, a resistive t structure can be used to define hysteresis values, also shown in figure?2 . after the desired ov and uv thresholds are set with resistors r8 through r10 , r11 and r12 are calculated using : r 1 1 = r 8 ? [ o v h y s ? i e x t ? ( r 9 + r 1 0 ) ] i e x t ? ( r 8 + r 9 + r 1 0 ) r 1 2 = ( r 8 + r 9 ) ? [ u v h y s ? i e x t ? r 1 0 ] i e x t ? ( r 8 + r 9 + r 1 0 ) where ov hys , uv hys are the desired ov and uv hyster - esis voltage magnitudes at v1 through v2 , and i ext is the programmed hysteresis current. the lt c4418 has an ov/uv fault filter time of t valid (off) . add a filter capacitor, c uvf , between the ov or uv pin and gnd to extend the fault filter time and ride through tran - sients as shown in figure?3 . by extending the filter time, the detection of a valid uv condition will also be delayed. to tailor the filter time delays individually, separate the single resistive divider into two resistive dividers. when selecting resistor values, take into consideration board leakage and ov/uv pin leakage and their affect on threshold accuracy. priority reassignment a connected input supply can be manually disconnected by artificially creating a uv fault. an example is shown in figure?3 . when n-channel mosfet, m2 , is turned on, the u v1 pin is pulled below 1v . the lt c4418 then disconnects v1 and connects the next highest valid priority to v out . alternatively, the vali d2 can be connected directly to u v1 to swap priority to channel 2, as shown in figure?12 . connect tmr to intv cc to ensure quick switchover to channel 1 when channel 2 becomes invalid. selecting external p-channel mosfets the lt c4418 drives external p-channel mosfets to conduct or block load current between an input supply and load. when selecting external p-channel mosfets, the key parameters to consider are : 1. on-resistance (r ds(on) ) 2. absolute max drain-source breakdown voltage (bv dss(max) ) 3. threshold voltage (v gs(th) ) 4. soa the on-resistance of each p-channel mosfet should be sufficiently low when conducting the maximum load current to minimize voltage drop and power dissipation. external p-channel mosfet devices may be paralleled to decrease resistance and decrease power dissipation of each paralleled mosfet. the clamped gate drive output is 4.5v (minimum) from the common source connection. select logic level or lower threshold external mosfets to ensure adequate overdrive. for applications with input supplies lower than the clamp voltage, choose external mosfets with thresholds suf - ficiently lower than the input supply voltage to guarantee full enhancement. lt c4418 rev a
15 for more information www.analog.com applications information it is imperative that external p-channel mosfet devices never exceed their bv dss(max) rating in the application. switching inductive supply inputs with low value input and/or output capacitances may require additional precau - tions ; see transient supply protection section for more information. in normal operation, the external p-channel mosfet de - vices are either fully on, dissipating relatively low power, or off, dissipating no power. however, during slew-rate controlled startup or switchover from a lower to a higher voltage with inrush current, significant power may be dis - sipated in the external p-channel mosfets. the external mosfets must satisfy the safe operating area (soa) curve for these conditions. a list of suggested p-channel mosfets is shown in table?1 . use procedures outlined in this section and the soa curves in the chosen mosfet manufacturer s data sheet to verify suitability for the application. table?1. listed of suggested p-channel mosfets mosfet app max op voltage v th(max) v gs(max) v ds(max) r ds(on) () s i4465 ady 5v C 1v 8v C 8v 0.009 at C 4.5v 0.011 at C 2.5v s i4931 dy 10v C 1v 8v C 12v 0.018 at C 4.5v 0.022 at C 2.5v i rf7220 10v C 0.6v 12v C 12v 0.012 at C 4.5v 0.02 at C 2.5v i rf7325 * 10v C 0.9v 8v C 12v 0.024 at C 4.5v 0.033 at C 2.5v fd s4465 18v C 1.5v 8v C 20v 0.0085 at C 4.5v 0.010 at C 2.5v fdm s6673 bz 28v C 3v 25v C 30v 0.0125 fd s6675 28v C 3v 20v C 30v 0.02 ao4803a* 28v C 2.5v 20v C 30v 0.074 s i4909 dy* 36v C 2.5v 20v C 40v 0.034 s ud50p04 -23 36v C 3v 20v C 40v 0.0117 s i7463 adp 36v C 3v 20v C 40v 0.0135 f dd4685 /fd s4685 36v C 3v 20v C 40v 0.035 s i7461 dp 40v C 3v 20v C 60v 0.019 fd mc5614 p 40v C 3v 20v C 60v 0.135 s ud50p06 -15 40v C 3v 20v C 60v 0.02 f dd5614 p 40v C 3v 20v C 60v 0.13 fd s9958 40v C 3v 20v C 60v 0.135 s ud50p08 -25l 40v C 3v 20v C 80v 0.029 s i7469 dp 40v C 3v 20v C 80v 0.029 fd s8935 40v C 3v 20v C 80v 0.247 s i7489 dp 40v C 3v 20v C 100v 0.047 *dual p-channel mosfets in a single package. lt c4418 rev a
16 for more information www.analog.com applications information selecting v out capacitance to ensure there is minimal droop at the output, select a low esr capacitor large enough to ride through the dead time between channel switchover. a low esr bulk capacitor will reduce ir drops to the output voltage while the load current is sourced from the capacitor. to calculate the value of the load capacitor that will ride through the break-before-make time, t g(switchover) during a normal switchover use : c o u t i l o a d ( m a x ) ? t g ( s w i t c h o v e r ) v o u t ( d r o o p ) ? e s r ? i l o a d ( m a x ) where i load(max) is the maximum load current drawn and v out(droop) is the maximum acceptable amount of voltage droop at the output. this equation assumes no inrush current limiting circuitry is required. if inrush cur - rent limiting is necessary then a modified equation for the minimum c out calculation is used : c o u t i l o a d ? t g ( s w i t c h o v e r ) + 0 . 7 9 ? r s ? c s ( ) v o u t ( d r o o p ) ? e s r ? i l o a d the selection of r s and c out is iterative. initially, the minimum c out is calculated by approximating : 0.79 ? r s ? c s = 15s once r s is determined, the selection of c out should be checked by substituting the values of r s and c s into the equation above to ensure the condition is satisfied. see the inrush current and input voltage droop section. for conditions where v1 /2 supplies are rapidly discon - nected or may be shorted then it is appropriate to add the vali d1 /2 off delay from ov/uv fault (t valid (off) ) to t g(switchover) in the previous equations. note that there is a trade-off between larger c out and tolerating higher inrush current. c o u t i l o a d ? t g ( s w i t c h o v e r ) + t v a l i d ( o f f ) + 0 . 7 9 ? r s ? c s ( ) v o u t ( d r o o p ) ? e s r ? i l o a d inrush current and input voltage droop when connecting a higher voltage supply to a lower voltage output, significant inrush current can occur while charging an output capacitor with low esr. inrush current during a switchover can cause two issues, (1) p-channel mosfets are subjected to damaging power dissipation and (2) an undesirable uv fault from significant input voltage droop also known as motor-boating. motor-boating is specifi - cally a concern when the uv hys threshold for the input supply connected to v1 is higher in voltage than the ov/ uv window of the input supply connected to v2 . motor- boating is prevented through inrush current limiting and ensuring that there is a proper amount of hysteresis to accommodate the expected input supply voltage droop. at a minimum hysteresis should provide enough margin for the input supply voltage to droop due to inrush and load current during switchover. select the ov/uv operation range appropriately. inrush current limiting is necessary in situations where one or more of these conditions apply : 1. max i inrush through the supply source resistance, r src can cause a uv condition. 2. peak inrush current violates the maximum pulsed drain current (i dm ) of the external p-channel mosfets. 3. large voltage differential between input supplies or the configured ov/uv thresholds between input supplies. 4. small or unknown source impedance. 5. large output capacitance. in order to check maximum expected inrush current use : m a x i i n r u s h = ( m a x v 1 o r v 2 ) ? v o u t ( m i n ) r s r c + e s r c o u t + 2 ? r d s ( o n ) where esr cout is the esr of the output capacitor and r ds(on) is the channel resistance of the selected p-channel mosfets. the maximum voltage differential is determined from the higher supply s ov threshold and the lower sup - ply s uv threshold minus v out droop. lt c4418 rev a
17 for more information www.analog.com applications information with the lt c4418 , inrush current can be reduced by slew rate limiting the output voltage. the gate driver can be configured to slew rate limit the output voltage with a resistor, capacitor and schottky diode, as shown in figure?4 . the series resistor, r s , and capacitor, c s , are inrush cur - rent limiting components, while the schottky diode, d s , provides a fast turn off path when g1 is pulled to v s1 . choose c s to be at least ten times the external p-channel mosfet s reverse transfer capacitance, c rss(max) , and c vs to be ten times c s . alternatively, c rss(max) itself can be used in place of c s , where its value is taken at the minimum v ds voltage. gate driver when turning a channel on, the lt c4418 pulls the com - mon gate connection ( g1 and g2 ) down with a strong low impedance pull-down. see i g(dn) in the electrical characteristics table. v s1 and v s2 voltages lower than 5v will result in lower gate slew rates, see the typical performance characteristics curves for more detail. after turning a channel on the gate driver holds down g1 or g2 with a small pull-down current sufficient to maintain the ? v g clamp voltage. clamping the g1 and g2 voltage prevents any overvoltage stress on the gate to source oxide of the external p-channel mosfets. when turning a channel off, the gate driver pulls the common gate to the common source with a switch having an on-resistance of r g(off) , to facilitate a quick turn-off. to minimize inrush current at start-up, the gate driver soft-starts the gate drive of the first input to connect to v out . the gate pin is regulated to create an approximately 4v /ms slew rate on v out . logic level p-channel mosfets with thresholds below 1v will result in faster soft-start slew rates on v out . slew rate control is terminated when any channel disconnects or a time period 35ms has elapsed. once soft-start has terminated, the gate driver operates nor - mally. a shdn low to high transition reactivates soft-start, provided v out drops below 2.3v before shdn is high. v out drooping below 1.7v also reactivates soft-start. selecting validation time the validation time is adjustable allowing greater flexibility when validating input supplies over a variety of applica - tions. the validation time, t valid , is adjusted by connecting a capacitor, c tmr , between the tmr pin and ground. the value of this capacitor is determined by : c t m r = t v a l i d 1 6 m s / n f it is not recommended to leave the tmr pin open, instead connect the pin to intv cc to engage fast mode operation where t valid is reduced to approximately 3.5s typical. the accuracy of the validation time is affected by capacitor leakage (the nominal charging current is specified by i tmr ) and capacitor tolerance. a low leakage ceramic capacitor is recommended. figure?4. inrush current limiting components with a desired c out and inrush current target the value of r s is : r s v g ( s i n k ) ? v g s ( ) ? c o u t c s ? i i n r u s h where ? v g(sink) is the lt c4418 s sink clamp voltage and v gs is the external p-channel s gate to source volt - age when driving the load and inrush current. the output load current i load is neglected for simplicity. when in - rush current limiting, ensure power dissipation does not exceed the manufacturer s soa for the chosen external p-channel mosfet. lt c4418 rev a c out LTC4418 vs1/2 g1/2 v out v1/2 v out 4418 f04 m1 m2 d s bat54 r s c s c vs c in
18 for more information www.analog.com applications information transient supply protection the lt c4418 s abrupt switching due to ov or uv faults can create large transient overvoltage events with induc - tive input supplies, such as supplies connected by a long cable. at times the transient overvoltage condition can exceed twice the nominal voltage resulting in damage to the system. it is imperative that external p-channel mosfet devices do not exceed their single pulse avalanche energy specification (eas) in unclamped inductive applications and input voltages to the lt c4418 never exceed the absolute maximum ratings . to minimize inductive voltage spikes, use wider and/or heavier trace plating. transient voltage suppressors (tvs) should be placed on supply pins, v1 and v2 where inductive transients beyond the 60v absolute maximum rating are expected. when selecting transient voltage suppressors, ensure the reverse standoff voltage (v r ) is equal to or greater than the application operating voltage, the peak pulse current (i pp ) is higher than the peak transient voltage divided by the source impedance, the maximum clamping voltage (v clamp ) at the rated i pp is less than the absolute maximum ratings and bv dss of all the external p-channel mosfets. see figure?5 . the lt c4418 s absolute maximum voltage rating for v1 and v2 allow it to withstand supply- side inductive voltage spikes up to 60v . a range of tvs diode specifications can be used accommodating v rwm ratings up to 36v and v clamp ratings up to 60v . reverse voltage protection the lt c4418 is designed to withstand reverse voltages applied to v1 and v2 with respect to v out up to C 84v . this allows v out to operate at or near its maximum operating voltage, 42v with v1 / v2 at a C 42v reverse voltage. the large reverse voltage rating protects input supplies and downstream devices connected to v out against high re - verse voltage connections of C 42v (absolute maximum) with margin. select p-channel mosfets with b vdss(max) ratings capable of handling any anticipated reverse volt - ages between v out and v1 or v2 . ensure transient volt - age suppressors (tvs) connected to reverse connection protected inputs ( v1 and v2 ) are bidirectional and input capacitors are rated for the negative voltage. see typical performance characteristics for voltage waveforms il - lustrating this feature. reverse current blocking when switching channels from higher voltages to lower voltages, the rev comparator verifies the v out voltage is below the connecting channel s voltage by 120mv before the new channel is allowed to connect to v out . v out is allowed to decay at a slew rate determined by the load current divided by the load capacitance. this ensures little to no reverse conduction occurs during switching. figure?5. transient voltage suppression lt c4418 rev a output parasitic inductance input parasitic inductance snubber or or tvs LTC4418 vs1/2 g1/2 v out c load 4418 f05 m1 m2 tvs c out r sn c sn c vin v1/2 v out
19 for more information www.analog.com applications information disabling all channels with en and shdn driving en below 1v turns off all external p-channel mosfets but does not interrupt input supply monitoring or reset the validation timers. driving en above 1v enables the highest valid priority channel to connect to v out . this feature is essential in cascading applications. for applica - tions where en could be driven below ground, limit the current from en with a 10k resistor. forcing shdn below 0.8v turns off all external p-channel mosfets, disables all ov and uv comparators and resets all validation tim - ers. vali d1 and vali d2 release high to indicate all inputs are invalid, regardless of the input supply condition. the lt c4418 is required to revalidate the input supplies before connecting the inputs to v out . for applications where shdn could be driven below ground, limit the current from shdn with a 10k resistor. if en or shdn are not used then each can be connected to intv cc . input supply and v out shorts input shorts can cause high current slew rates. coupled with series parasitic inductances in the input and output paths, potentially destructive transients may appear at the input and output pins. if the short occurs on an input that is not powering v out , the impact to the system is benign due to the p-channel mosfets having reverse block capability. if a short occurs on an input that is power - ing v out , the issue is compounded by high conduction current and low impedance connection to the output via the p-channel mosfets. once the lt c4418 blocks the high input short current, v1 and v2 may experience large negative voltage spikes while the output may experience large positive voltage spikes. if v out is shorted there will be an input supply uv fault due to its low impedance connection. if the uv threshold is high enough and the short resistive enough, the lt c4418 will disconnect the input. if the other input supply is valid it will attempt to connect. rapid switching between sup - plies may occur if t valid is configured to be too short in duration or in fast mode. the fast change in current may force the output below gnd, while the input will increase in voltage. if uv thresholds are set close to the minimum operating voltage of the lt c4418 , it may not disconnect the input from the output before the output is dragged below the operating voltage of the lt c4418 . placing a bypass capacitor from intv cc to gnd keeps the internal rail of the lt c4418 from collapsing due to these types of transients. to prevent damage to the lt c4418 and associated devices in the event of an input or output short, it may be necessary to protect the input and output pins as shown in figure?5 . protect the input pins with either unidirectional or bidirec - tional tvs and v out with a unidirectional tvs. in situations where v out has the potential to get pulled below ground place a reverse schottky diode from v out to gnd or a small series resistance with the v out pin to limit current. an input and output capacitor between 0.1f and 10f with intentional or parasitic series resistance will aid in dampening voltage spikes. cascading the lt c4418 is cascadable and can work in conjunction with the lt c4417 to prioritize three or more input sup - plies. when cascading multiple lt c4418 s, connect v out pins together and connect each lt c4418 cas pin to the next lower priority lt c4418 s en pin. see figure?6 . the first lt c4418 to validate an input will soft-start the com - mon output. once the output is above 2.5v , power will be drawn from v out by the other lt c4418 regardless of its supply connections. when the master lt c4418 wants to connect one of its input supplies to the v out , it simultane - ously initiates a channel turn on and pulls its cas pin low to force the slave lt c4418 to disconnect its channels. a small amount of reverse conduction may occur in this case. the amount of cross conduction will depend on the total turn-on delay of the master channel compared with the turn-off delay of the slave channel. care should be taken to ensure the connection between cas and en is as short as possible, to minimize the capacitance and hence the turn-off delay of the slave channel. when all of the inputs to the master lt c4418 are invalid, the master confirms that all its inputs are disconnected from v out before releasing cas. cas is pulled to the intv cc rail with a 20a current source, allowing the slave lt c4418 rev a
20 for more information www.analog.com applications information lt c4418 to connect its highest valid priority channel to v out . confirmation that all channels are off before the slave is allowed to connect its channel to v out prevents cross conduction from occurring. driving the master lt c4418 s en low forces both master and slave to disconnect all channels from the common output and continue monitoring the input supplies. driv - ing the master lt c4418 s shdn low places it in a reset state where all of its channels are disconnected and cas is pulled high with a 20a current source, allowing the slave lt c4418 to become the master and connect its highest valid priority channel to the common output. design example in this example, the lt c4418 prioritizes between 5v and 12v supplies for a 1.25a system as shown in figure?7 . power is only sourced from the 12v supply when the 5v supply is invalid. the 12v supply has a 20m ? source resistance (r src ) and the ambient conditions of the system are between 25 c and 85 c . the design must accommodate 2.5% tolerance on the 5v supply and a 10% tolerance on the 12v supply and limit the v out droop to 500mv during switchover. the load capacitor is assumed to be an electrolytic with a minimum esr (esr cout ) of 25m ? at 25 c . determining ov/uv windows for the 5v v1 supply, 2.5% tolerance sets an operational window of 4.875v to 5.125v . in order to accommodate this voltage range the ov/uv thresholds must allow for desired hysteresis, external resistive divider error and comparator threshold error. for the 5v v1 supply, an additional 2.5% error is included for margin which means that the ov/uv window must accommodate 4.75v to 5.25v range. for 5% external hysteresis or 250mv , set the u v1 = 4.5v and o v1 = 5.5v . for the 12v v2 supply, taking into account supply tolerance and a margin for error sources the operational window is 10.2v to 13.78v . since external hysteresis is used, channel 2 also has 250mv of hysteresis ( 2.1%). the ov/uv thresholds are u v2 = 9.95v and o v2 = 14.03v . these thresholds determine the maximum possible dif - ferential voltage between supplies at switchover. + figure?6. cascaded application lt c4418 rev a en shdn disable all channels shdn master 2 supplies master 2 supplies slave 1st priority supply 2nd priority supply 4th priority supply 3rd priority supply m3 m1 m2 vs1 g2 m5 m6 LTC4418 slave vs5 g6 v out m4 en shdn m7 m8 vs7 g8 4418 f06 v out c out LTC4418 master cas to en connection vs2 g2 v out cas
21 for more information www.analog.com applications information figure?7. design example schematic 5v / 12v system channel 1 2 uv threshold 4.5v 9.95v ov threshold 5.5v 14.13v hysteresis 250mv 250mv inrush limit C 12a validation delay 16ms 16ms v out droop max 500mv v2 uv2 ov2 LTC4418 4418 f07 vs1 g1 vs2 g2 r3 1m c vs1 100nf r2 53.6k r1 232k r6 1m r5 33.2k r4 78.7k c vs2 470nf ds bat46wj m3 m4 c s 47nf r s 698 r7 100k v1 invalid v2 invalid c out 82f 25m esr v out 1.25a v1 uv1 ov1 v out valid1 valid2 cas intv cc en shdn tmr + c in1 10f + c in2 10f + fds4465 m1 m2 fds4465 5v sys 12v wall adapter input impedance: 20m gnd c v1 100nf c v2 100nf hys r hys 255k c tmr 1nf c intvcc 100nf r8 100k lt3060-3.3 lt c4418 rev a
22 for more information www.analog.com applications information p-channel mosfet selection using the list of suggested p-channel mosfets in table?1 as a guideline, the fd s4465 (max v ds = C 20v , r ds(on) = 8.5m ? ) is appropriate for this application. when selecting external mosfets the following items are relevant : 1. max v ds 2. r ds(on) 3. idm 4. c rss (maximum) 5. v gs (at i inrush + i load current) 6. soa inrush current component selection the u v2 threshold for v2 is larger than the ov/uv window of v1 . this means that there could be significant inrush current during switchover from v1 to v2 . there are two inrush current issues to address : 1. avoid damaging the p-channel mosfets by violating their idm specification 2. prevent uv faults on channel 2 from v2 input droop the maximum inrush current occurs when switching to the v2 supply which has a maximum voltage of 14.03v . the minimum voltage of v out is 4.5v if v1 is at its uv threshold. for these conditions, the maximum inrush current through the p-channel mosfets is : m a x i i n r u s h = v 2 ( m a x ) ? v o u t ( m i n ) r s r c + e s r c o u t + 2 ? r d s ( o n ) = 1 4 . 0 3 v ? 4 . 5 v 0 . 0 2 + 0 . 0 2 5 + 0 . 1 7 = 1 5 4 a the 154a worst case inrush current far exceeds the 50a idm spec of the fd s4465 . the worst case condition for generating a uv fault on channel 2 is if v2 is just above uv hys threshold of 10.2v . given the input impedance of 20m ? , the maximum tolerable inrush current is : t o l e r a b l e i i n r u s h = u v h y s 2 r s r c = 2 5 0 m v 0 . 0 2 = 1 2 . 5 a based on these calculations, the target inrush current for the v2 powerpath switches is 12a . now the appropriate values for output capacitance and inrush current limiting components are determined. the first step is to calculate the minimum required output capacitance, c out , to satisfy the desired output voltage droop, 500mv . assume the inrush current limiting com - ponents, r s and c s , add 15s to the switchover time. c o u t i l o a d ? t g ( s w i t c h o v e r ) + 1 5 s ( ) v o u t ( d r o o p ) ? e s r c o u t ? i l o a d 1 . 2 5 a ? ( 2 . 7 s + 1 5 s ) 5 0 0 m v ? 1 . 2 5 a ? 2 5 m 4 7 f for aluminum electrolytic capacitors add at least 20%. for margin, choose 82f for c out for this application. the inrush current limiting components must now be determined. information from the fd s4465 data sheet required is v gs at i inrush + i load which is 1.25v at ap - proximately 12a and the maximum value of c rss which is 4000pf . the minimum value of c s is 10 ? c rss or 40nf so a 47nf c s value is selected. next calculate r s using the maximum specification for ? v g(sink) : r s ( v g ( s i n k ) ? v g s ) ? c o u t c s ? i i n r u s h ( t a r g e t ) ( 6 v ? 1 . 2 5 v ) ? 8 2 f 4 7 n f ? 1 2 a 6 9 0 . 6 where the closest 1% value is 698 ? . with the inrush current limiting components known, the desired output capacitance is checked with the equation : c o u t i l o a d ? t g ( s w i t c h o v e r ) + 0 . 7 9 ? r s ? c s ( ) v o u t ( d r o o p ) ? e s r ? i l o a d 1 . 2 5 a ? ( 2 . 7 s + 0 . 7 9 ? 6 9 8 ? 4 7 n f ) 5 0 0 m v ? 2 5 m 7 1 . 5 4 f the selected 82f output capacitance is therefore suit - able. a typical value for c v s1 and c v s2 is 0.1f . for the situation where inrush current limiting components are used, so c v s2 is chosen to be 0.47f . lt c4418 rev a
23 for more information www.analog.com applications information external p-channel mosfet power dissipation the soa of the p-channel mosfet should be checked to ensure it is not violated. worst case channel turn on time for the v2 power path occurs for the same condition used to determine inrush current limiting components for a maximum inrush current of 12a . d t = v 2 ( m a x ) ? v o u t ( m i n ) ( ) ? c o u t i i n r u s h ( t a r g e t ) = ( 1 4 . 0 5 v ? 4 . 5 v ) ? 8 2 f 1 2 a = 6 2 s checking the maximum safe operating area plot in the fd s4465 data sheet shows that it must withstand 12a at 10v worst case ( 120w ) for 62s . the soa plot for the fd s4465 shows that it can conduct 50a at 10v ( 1kw ) for 100s satisfying the requirement. the maximum safe operating area plot can also be checked with regard to the soft-start power dissipation. setting operational range the 5v supply has a 2.5% operational window in this example. the thresholds chosen give an additional 2.5% margin in each direction. instead of using the internal fixed 150mv (or 3%) hysteresis, the higher priority 5v supply is set for 250mv hysteresis using an external hys - teresis current (i ext ) of 250na . the resistive divider will be configured as a three-resistive network. first select an appropriate r hys value : r h y s = 6 3 m v 2 5 0 n a = 2 5 2 k where the closest 1% value is 255k ? . i e x t = 6 3 m v 2 5 5 k = 2 4 7 n a r3 is calculated from : r 3 = d e s i r e d h y s t e r e s i s i e x t = 2 5 0 m v 2 4 7 n a = 1 0 1 2 k where the closest 1% value is 1000k ? . next, calculate r1 from : r 1 = v t h o v 1 ? 1 u v 1 / v t h ( ) ? 1 + 1 ? ? ? ? ? ? ? ? ? r 3 = 1 v 5 . 5 v ? 1 4 . 5 v / 1 v ( ) ? 1 + 1 ? ? ? ? ? ? ? ? ? 1 m = 2 3 3 . 7 k where the closest 1% value is 232k . r2 can be calculated from : r 2 = r 3 ( u v 1 / v t h ) ? 1 ? r 1 = 1 m ( 4 . 5 v / 1 v ) ? ? 2 3 2 k = 5 3 . 7 k where the closest 1% value is 53.6k . the actual uv threshold is : u v 1 = v t h ? r 1 + r 2 r 3 r 1 + r 2 = 4 . 5 v u v 1 h y s = r 3 ? i e x t = 1 m ? 2 4 7 n a = 2 4 7 m v likewise, the actual ov threshold is : o v 1 = v t h ? r 1 + r 2 + r 3 r 1 = 5 . 5 4 v o v 1 h y s = ( r 2 + r 3 ) ? i e x t = ( 1 1 3 k + 1 m ) ? 2 4 7 n a = 2 6 0 m v the values of r4 through r6 are calculated similarly using the configured hysteresis current. if internal hysteresis is desired, the resistor values for a three-resistive network can be determined by initially selecting resistive divider current and using it to determine r1 - r3 or r sum . the choice of resistive divider values should take into consideration board and ov/uv pin leakages. the hysteresis thresholds are calculated by : u v ( r i s i n g ) = v t h + v h y s ( i n t ) ( ) ? r s u m r 1 + r 2 u v ( f a l l i n g ) = v t h + v h y s ( i n t ) ( ) ? r s u m r 1 lt c4418 rev a
24 for more information www.analog.com applications information figure?8. lt c4418 layout example tmr uv1 ov1 uv2 ov2 v out vs1 g1 vs2 g2 hys shdn en v1 v2 vallid1 valid2 gnd cas intv cc 20 19 18 17 16 6 7 8 gnd 21 9 10 5 4 3 2 1 11 12 13 14 15 using internal hysteresis in this application would result in 130mv uv hysteresis and 170mv ov hysteresis for v1 . likewise, the v2 ov/uv window would result in 300mv uv hysteresis and 420mv ov hysteresis. layout consideration high current applications demand careful attention to trace resistances. sheet resistance of 1oz copper is ~ 530 ? per square. keep high current traces short with minimum trace widths of 0.02" per amp to ensure traces stay at a reasonable temperature. using 0.03" per amp or wider is recommended. to improve noise immunity, place ov/uv resistive dividers as close to the lt c4418 as possible. transient voltage suppressors should be located as close to the input connector as possible with short wide traces to gnd. figure?8 shows a partial layout that addresses these issues. dual 28v system with kelvin sense connection through connector the dual 28v supply system in figure?13 includes a back - plane connector with a kelvin sense. the supply pin and resistive divider network for each channel are connected to the kelvin sense. a rapid disconnection of one of the input supplies from the backplane causes an immediate uv fault since the time constant at v1 /2 and the respective ov/uv pins is much shorter than at the output. without a kelvin sense connection the input supply must discharge down to its uv threshold over a period of time before switchover. both input supplies include transient voltage suppression diodes (smb j36 ca) rated for 36v operation and a clamping voltage of 58v . lt c4418 rev a cvs2 cvs1 cv1 m1 m2 m3 m4 cs1 0.03" per ampere transient voltage suppressor from v1 input source ctmr r1 r3 r6 r4 cv2 rhys s rs1 ds1 from v2 input source g g s d d g s d s g gnd d r2 r5 gnd 4418 f08 to output note: not to scale c intvcc
25 for more information www.analog.com typical applications figure?9. dual 5v system v2 uv2 ov2 LTC4418 4418 f09 vs1 g1 vs2 g2 r3 1.15m r2 82.5k r1 255k r6 1.15m r5 82.5k r4 255k c vs2 470nf c vs1 470nf m3 m4 r7 100k sysa invalid sysb invalid c in3 82f 25m esr v out 1.5a max c s2 47nf d s2 bat46wj v1 uv1 ov1 v out valid1 valid2 cas intv cc en shdn tmr + si4465dy m1 m2 si4465dy 5v 2.5% sys a imput impedance: 25m 5v 2.5% sys b imput impedance: 25m gnd c v1 100nf hys r hys 210k c tmr 1nf c intvcc 100nf r s2 422 r8 100k c v2 100nf c in1 10f + c in2 10f + c s1 47nf ds1 bat46wj r s1 422 channel 1 2 uv threshold 4.4v 4.4v ov threshold 5.85v 5.85v hysteresis 350mv 350mv inrush limit 25a 25a validation delay 16ms 16ms v out droop max 400mv lt c4418 rev a
26 for more information www.analog.com typical applications figure?10. 5v usb and aa alkaline battery backup v2 uv2 ov2 LTC4418 4418 f10 vs1 g1 vs2 g2 r3 402k r2 30.9k r1 90.9k r6 402k r7 562k r5 76.8k r4 78.7k c vs2 0.1f c vs1 0.1f m3 m4 r9 1m v1 invalid v2 invalid c out 33f 30m esr v out 500ma max v1 uv1 ov1 v out valid1 valid2 cas intv cc en shdn tmr + irf7325 m1 m2 irf7325 5v usb 4 aa batteries gnd c v1 0.1f hys r hys 255k c intvcc 100nf c tmr 1nf r10 1m c v2 0.1f c in1 10f + v bat input impedance: 900m r8 105k channel 1 2 uv threshold 4.3v 3.6v ov threshold 5.76v 7.1v hysteresis 100mv 600mv (uv) 300mv (ov) inrush limit C C validation delay 16ms 16ms v out droop max 500mv lt c4418 rev a
27 for more information www.analog.com typical applications figure?11. 12v system with 24v backup supply v2 uv2 ov2 LTC4418 4418 f11 vs1 g1 vs2 g2 r3 634k c vs1 100nf r2 23.2k r hys 158k r1 49.9k r6 634k r5 11.8k r4 23.2k c vs2 220nf r s 1.96k ds bat46wj m3 m4 c s 6.8nf r7 1m 12v invalid 24v invalid c out 39f 30m esr v out 2a max v1 uv1 ov1 v out valid1 valid2 cas intv cc en shdn tmr + c in1 39f + c in2 39f + fds4685 m1 m2 fds4685 12v sys 24v sys input impedance: 30m gnd c vs1 100nf c v2 100nf hys c tmr 1nf c intvcc 100nf r8 1m lt3060-3.3 channel 1 2 uv threshold 9.67v 19.17v ov threshold 14.17v 28.84v hysteresis 250mv 250mv inrush limit C 8a validation delay 16ms 16ms v out droop max 1.2v lt c4418 rev a
28 for more information www.analog.com typical applications figure?12. dual 24v system with priority swapped v2 uv2 ov2 LTC4418 4418 f12 vs1 g1 vs2 g2 r3 1.87m c vs1 68nf r2 34.8k r1 68.1k r6 1.87m r5 34.8k r4 68.1k c vs2 68nf r s2 133 ds2 bat46wj m3 m4 c s2 6.8nf r7 100k v1 invalid ch priority swap c out 10f 120m esr v out 1a max v1 uv1 ov1 v out valid1 valid2 intv cc en shdn tmr + c in1 47f + c in2 47f + fdd4685 m1 m2 fdd4685 24v sys a input impedance: 30m 24v sys b input impedance: 30m gnd c v1 100nf c v2 100nf hys c intvcc 100nf r hys 158k lt3060-3.3 r s1 133 ds1 bat46wj c s1 6.8nf channel 1 2 uv threshold 19.17v 19.17v ov threshold 29v 29v hysteresis 750mv 750mv inrush limit 50a 50a validation delay 3.5s 3.5s v out droop max 2.4v ch priority is swapped - fast mode required lt c4418 rev a
29 for more information www.analog.com information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. revision history rev date description page number a 04/18 updated specification conditions : r g(off) , t ss , i tmr 3, 4 package description please refer to http : //www.linear.com/product/ lt c4418 #packaging for the most recent package drawings. 4.00 0.10 4.00 0.10 note: 1. drawing is proposed to be made a jedec package outline mo-220 variation (wggd-1)?to be approved 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 20 19 1 2 bottom view?exposed pad 2.00 ref 2.45 0. 10 0.75 0.05 r = 0.115 typ r = 0.05 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uf20) qfn 01-07 rev a recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 0.50 bsc 2.00 ref 2.45 0 . 05 3.10 0.05 4.50 0.05 package outline pin 1 notch r = 0.20 typ or 0.35 45 chamfer 2.45 0. 10 2.45 0 . 05 uf package 20-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1710 rev a) lt c4418 rev a
30 for more information www.analog.com d16838-0-4/18(a) www.analog.com ? analog devices, inc. 2017-2018 related parts typical application figure?13. dual 28v system with kelvin sense connection through connector part number description comments lt c4411 2.6a low loss ideal diode in thinsot ? internal 2.6a p-channel, 2.6v to 5.5v , 40a i q , sot-23 package lt c4412 36v low loss powerpath controller in thinsot 2.5v to 36v , p-channel, 11a i q sot-23 package lt c4415 dual 4a ideal diodes with adjustable current limit dual internal p-channel, 1.7v to 5.5v , msop-16 and dfn-16 packages lt c4416 36v low loss dual powerpath controller for large pfets 3.6v to 36v , 35a i q msop-10 package lt c4417 3- channel prioritized powerpath controller triple p-channel controller, 2.5v to 36v , ssop-24 and qfn-24 packages lt c4419 / lt c4420 18v dual input micropower powerpath prioritizer internal p-channel, 1.8v to 18v , 3.6a i q , dfn-12 and msop-12 packages lt c4355 positive high voltage ideal diode-or dual n-channel, 9v to 80v , so-16, msop-16 and dfn-14 packages lt c4359 ideal diode controller with reverse input protection n-channel, 4v to 80v , msop-8 and dfn-6 packages channel 1 2 uv threshold 22.4v 22.4v ov threshold 33v 33v hysteresis 3% ov/uv 3% ov/uv inrush limit 10a 10a validation delay 16ms 16ms v out droop max 2.8v v2 uv2 ov2 LTC4418 4418 f13 vs1 g1 vs2 g2 r3 1.33m c vs1 470nf 100v r2 20k r1 42.2k r6 1.33m r5 20k r4 42.2k c vs2 470nf 100v r s2 243 d s2 bat46wj m3 m4 c s2 47nf r7 100k v1 invalid v2 invalid c outa 22f 50v 170m esr v out 3.5a v1 uv1 ov1 v out valid1 valid2 intv cc en shdn tmr + tvs1 smbj36ca kelvin kelvin sud50p06 m1 m2 sud50p06 28v sys input impedance: 30m 28v backup input impedance: 30m gnd c v2 100nf 100v c v1 100nf 100v hys c intvcc 100nf c tmr 1nf r8 100k lt3060-3.3 tvs2 smbj36ca r s1 243 d s1 bat46wj c s1 47nf connector 4 connector 2 connector 3 connector 1 c outb 22f 50v 170m esr + lt c4418 rev a

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